The present invention relates to a semiconductor memory device including an equalizing circuit fitted to shorten a memory cycle time in particular.
In recent years, there has been a growing demand for achieving the high performance of a dynamic memory device and a stricter demand for the shortening of its cycle time in particular. As shown in FIG. 1, the cycle time of the dynamic memory device is defined by a minimal requisite active time plus a minimal requisite precharging time. How these two should be shortened has been a technical task to be achieved.
Further shortening of the minimal requisite active time of the above-mentioned cycle time also means the shortening of an access time of the memory device and many systems have conventionally been designed to achieve this task.
On the other hand, attempts to further shorten the minimal requisite precharging time of the cycle time have currently attracted not too much attention in spite of its importance the same as the former task.
FIG. 2 is a block circuit diagram showing a major section of an ordinary DRAM including equalizing transistors. Generally, the precharging time of the dynamic memory device is set in a manner as will be set out below. That is, the precharge time is set with a time from a "write level" (generally a voltage level determining a "0" or a "1" logical level) state, that is, a state in which a bit line BL is placed by the restoring (rewriting) operation of a sense amplifier SA after information (data) of a given memory cell MC has been read onto that bit line BL, to a state in which the bit line level is balanced to a given potential VBL, by the operation of an equalizing transistor ET, with a word line set in a read-ready state, that is, in an inactivated state (a row decoder set in the inactivated state) in which case the word line controls the transfer gate of the memory cell. The equalizing transistor ET is ON-controlled by an equalizing signal EQS from an equalizing control circuit EC.
In the above-mentioned ready state, the controlling of the equalizing transistor may be achieved by an equalizing signal for satisfying a predetermined time with which the bit line level is balanced through the equalizing signal. In actual practice, however, a longer time than the predetermined time is set as the precharging time, the reason of which will be given below.
FIG. 3 is a block circuit diagram showing an outline of the conventional semiconductor memory device. A RAS buffer 11 receives an external RAS signal (low active signal), and produces an internal signal (internal RAS signal). Upon receipt of the internal RAS signal an address buffer 12 supplies an externally received address signal to a predecoder 13. The predecoder 13 produces a signal X-ADR corresponding to the address signal. The signal X-ADR is used to select a corresponding one of divided memory cell arrays 14 which includes a cell to be accessed. A delay circuit 15 is so arranged as to control a decode timing of each word line and the internal RAS signal is such that it is delayed until column-based control becomes stable. The output of the delay circuit 15 emerges as a word line active signal WLact for controlling the activation/inactivation of the word line.
An equalizing control circuit 80 corresponds to the equalizing control circuit EC in FIG. 2. The equalizing control circuit 80 receives the internal RAS signal, signal WLact and signal X-ADR. The equalizing control signal EQS controls an equalizing circuit 17. The equalizing circuit 17 includes equalizing transistors, as shown in FIG. 2, to set a given potential on the bit line in a balanced state. The equalizing transistors are ON-controlled by the equalizing signal EQS. After the equalization is effected by the equalizing transistors, a predetermined voltage is applied to a control node (the gate of the transistors of associated memory cells MC) of the associated memory cells on a selected one of respective rows (word lines WL) and the transfer node of those memory cells on a selected one of those associated columns (bit line BL) is activated to allow a transfer of data signals into and out of the memory cell array.
Of the row-and column-base decoder 18, the row-base decoder 18 alone is shown as a block diagram. Through the activation of the word line active signal WLact, the divided memory cell array 14 to be activated is selected in accordance with the received internal address signal and a decoding operation is performed.
FIG. 4 is a circuit diagram showing a conventional arrangement of the above-mentioned equalizing control circuit 80 and FIG. 5 shows a timing chart relating to the circuit operation of FIG. 4. Here, the cycle time is such that RAS (internal RAS) in the memory corresponds to the external RAS (low active).
The equalizing control circuit of FIG. 4 will be explained below with reference to FIG. 5. A NOR gate 81 receives a signal WLact and internal RAS signal as two input signals and an AND gate 83 receives an inverted replica of an output signal of the NOR gate 81 via an inverter 82 and a signal X-ADR as two input signals and, through this combination logical array, an output signal of the AND gate 83 is passed through series-connected inverters 84 and 85 to provide an equalizing signal EQS.
That is, an equalizing operation is inactivated with the signal X-ADR and internal RAS signal both in the states (87) as shown in FIG. 5 and the equalizing operation is activated with the internal RAS signal set in an inactivated (low level signal) state (88) and the word line active signal set in a low level signal state (88) as shown in FIG. 5 so that the corresponding memory cell may be inactivated.
In the above-mentioned arrangement, in order to perform the equalizing operation, both a condition under which the word line active signal is set in the inactivated (low level) state to allow the word line to be inactivated and a condition under which the internal RAS signal is set in the inactivated (low level) state have to be satisfied and, once these conditions are satisfied, an equalizing operation is started.
In the arrangement as set out above, if the precharging time is set shorter on the memory device as indicated, for example, in FIG. 5, an equalizing operation to be performed originally from an inactivated state in which the word line is set is not done because the internal RAS signal has already been set, at that time, to an activated state and, hence, no proper logic is taken between the two (89).
In the prior art, in order to achieve further shortening of the precharging time, it may be possible to perform an adequate equalizing operation by activating an equalizing signal until a word line is activated and, in spite of this fact, the above-mentioned case is such that the equalizing signal is prepared from such a combination logic circuit arrangement, there being a risk that an equalizing signal will not be obtained adequately. Therefore, there is room for further improvement.